Analog digital data system



July 27, 1965 w. T. wYNNE ANALOG DIGITAL DATA SYSTEM 6 Sheets-Sheet 1Filed Feb. 25, 1962 mvN UMN

m mm

HMTN

July 27, 1965 Filed Feb. 23 1962 W. T. WYNNE NALOG DIGITAL DATA SYSTEM 6Sheets-Sheet 2 July 27, 1965 w. T. wYNNE ANALOG DIGITAL DATA SYSTEM 6Sheets-Sheet 3 Filed Feb. 23. 1962 .mm 350 EPE wN mm+mv 35m o...

mQ m a Nk" ...n

July 27, 1965 w. T, WYNNE 3,l97,622

ANALOG DIGITAL DATA SYSTEM Filed Feb. 23. 1962 6 SheetS-Sheet 4 'q E' LLFrom Amp. 22

IZO

July 27, 1965 w.'T. wYNNE ANALOG DIGITAL DATA SYSTEM 6 Sheets-Sheet 5Filed Feb. 25, 1962 Om 0 MN Scan.

July 27, 1965 w. T. wYNNE ANALOG DIGITAL DATA SYSTEM 6 Sheets-Sheet 6Filed Feb. 23, 1962 Sov'mo UNN mNN Ov 1,155 BoTmo v ov Qll LJ UnitedStates Patent f 3,l97,622 ANALUG DHGITAIL DATA YSTEM William T. Wynne,Willow Grove, Pa., assignor to Leeds and Northrop Company, Philadelphia,Pa., a corporation of Pennsylvania Filed Feb. 2.3, 1962, Ser. No.174,942 7 Claims. (Cl. 235-154) This invention relates to analog-digitalarithmetic systems for producing a binary-coded decimal outputrepresentative of the average of a predetermined number of analogValues, each representative for example of the output of a transducerresponsive to the magnitude of a condition such as temperature,pressure, rate of Llow, electrical generation or other process variable.

In accordance with the invention, each of successive analog Values iselfectively divided by two factors whose product equals thepredetermined number of analog Values whose average is to beascertained. Specifically, each analog value is first divided by one ofsaid factors by appropriately setting the gain of a scaling amplifierwhose output is converted to binary-coded form. A second division, bythe other of said factors, is eifected by setting the once dividedinstantaneous value as converted to binary-coded form in a register indispiaced position, the extent of displacernent corresponding with theorder of the second factor: more specifically, when the ampliiier outputis in binary-coded decimal form, its displacement in the registercorresponds with a division by per stage. Each of such twice dividedinstantaneous Values as set in the register is Combined with theaccumulation of such previously divided Values until the predeterininednumber thereof has been reached, at which time the registercontents'correspond with the average of the instantaneous Values. Whenthe actual instantaneous analog value is to be ascertained, theamplifier gain is set to uni'ty and there is no displacement of theamplifier output as set into the register. Both the actual instantaneousanalog value and the average analog value appear on the same outputlines of the register although, of course, at diiferent times.

Further in accordance with the invention, an analogto-digital Converterinterposed between the scaling arnplifier and the register converts theanalog input of the converter into sequentially-produced groups ofpulses, the number of the pulse groups corresponding with the number ofsignificant figures in the maximum analog value and the number of pulsesper group corresponding with the decimal value of the correspondingdigit of the actual analog value.

Further in accordance with the invention, the binarycoded counter stagesof the register each includes a counter-advance module comprising threeinput And gates and a diferentiator for producing a delayed output of anassociated amplifier. This module as used in a counter stage havingshift-steering lines has an additional input line which inhibits themodule from producing an output while the shift-steering iines areenabled so to prevent a false count in the stage.

The invention further resides in an analog-digital arithmetic system andComponents thereof having features of novelty and utility hereinafterdescribed and claimed.

For a more detailed understanding of the invention, reference is made tothe following detailed description and to the associated drawings inwhich:

FIGS. IA, IB jointly disclose in schematic form a complete systemembodying the invention;

FIG. IC is an explanatory figure more fully showing scanning switches ofthe systems of FIGS. 1A, IB, and FIG. 2;

FIG. 2 is a modification of the system of FIGS. 1A, IB;

WZZ Patented July 27, 1955 FIS. 3 shows the internal circuitry of ananalog-todigital converter included in the systems of FIGS. lA, lB andFIG. 2;

FIG. 4 discioses the internal circuitry of one of the register stages ofFIG. 2;

FIG. 5 is a circuit diagram of one of the counter-stage modules of FIG.4;

6 is a circuit diagram of the counter-advance modules of FiGS. 4 and 7;

FG. 7 discloses the Components of one stage of the register of FIG. IB;and

FIG. 8 is a circuit diagram of a common module of FIG. 7.

Referring to FIG. lA, the pulse generator it), which may be of anysuitable type such as a free-running multivibrator, continuouslyproduces timed pulses which are applied to the ring counter ll's orequivalent stepping switch. For each of its cycles, the stepping switchproduces in succession four signais A-D respectiveiy appearing on itsoutput lines f to 15.

The first of these signals, signal A, is applied over line 112 to thecontrol device or scanner 16 to advance by one step the position of themovable contacts 1'7A 1'7D of the four scan switches lSA-liD and also toset the gain-control resistance means 19, Zt') of the amplifiers 21, 22.The gain-control feedback resistors 19, 29 may be set, as by dials, topredetermined vaiues, or each may lcomprise a series of binary-codedresistors selectively included in circuit by a plurality of relayspreset for a predetermined pattern of operation by scanner JK. Theamplifiers 21, 22, as later explained, are provided to amplify topredeterrnined extent the output signals of conditionresponsive devicesor transdncers ZBA et seq. (FIG. IC) successively connected thereto byscan switch ItA in each cycle of scanner 16, each after a predeterminednumber of cycies of the stepping switch lil.

The second signal, signal B, produced by stepping switch 11 in each ofits cycles is applied, except for the #0 or homing position of the scanswitches, over lines 13 and HA as a Start signal for theanalog-to-digital Converter (hereinafter referred to as ADC). It is alsoapplied over line 1313 for every #2 position of scan switch lSB to theone-shot multivibrator circuits MA, 243 to effect a predetermined shiftof the digits then temporarily stored in the counter register 25 (FIG.IB). For every #3 position of scan switch 18B, signal B is applied overline BC to the flip-fiop circuits Z6A-26C to effect a differentpredetermined shift of the digits then temporarily stored in the counterregister 25. For every #2 position of scan switch lC, signal B isapplied over line 13D to the output gates 27 (FIG. lB) of accumulator 23which may, as shown, be of the register type or may be of the corememory type or of the magnetic drum type. For every #3 position of scanswitch 130, signal B is applied over line 1315 to the output gates 29 ofa second accumulator 39 of type similar to accumulator 2,8. The thirdsignal, signal C, produced by stepping switch 11 during each of itscycles, is applied over line MA for every #1 position of the scan switch131) to the input gates 31 of a readout device 34 (FIG. 1B). For every#2 position of scan switch ISD, the signal C is applied over line MB asan input pulse to the pulse counter 32. For every #3 position of sc-answitch 18D, the signal C is applied over` line MC as an input pulse tothe pulse counter 33.

The fourth signal, signal D, produced by stepping switch 11 during eachof its cycles, is applied over line 15 as a Reset signal for theregister 25.

For purpose of explanation of Operation of the system of FIGS. 1A, IB,it will be assumed that it is desired to read out the existing output ofa transducer 23A at one minute intervtals, to read out the average ofsuch output at hourly intervals, and to read out the average of suchatomene output for the preceding twenty-four-hour interval. In suchcase, the repetition frequency of the pulse generator is preselected, bydesign or adjustment, so that once per minute the switches f'dA-ISD scanthe #1 to #3 positions related to transducer ZSA: the counter 32 ispreselected, by design or adjustment, to produce one output pulse per 60input signals C: and counter 35 is preselected, by design or adjustment,to produce one output pulse per 1440 input signals C.

With the scan switches in their #1 positions as advanced thereto by asignal A for direct read-out of the existing output of transducer ZA,the gain of the amplifier 22 has been set by the scanner 16 to unity sothat the analog input of Converter 35 corresponds with the output oftransducer ZSA as ampliied by lamplifier Zl. For utilization of themaximum capabilities of the system and for Working with signal levelsabove the inherent noise of Converter 35, the gain of amplier Zll ispreset so that for maximum output of the transducer within its workingrange, the corresponding value stored in the register 25 will be nearlythe register maximum, i.e., 9999.

To give a specific example, it will be assumed that the transduceroutput is 7.359 millivolts (within its range of to 9.999 millivolts).With the gain of amplifier 21 being set at 1,000 and the gain ofamplifier 22 set at unity, the analog input to the Converter is 7.359vol-ts. During the ensuing cycle of the Converter as initiated by a Bsignal, such analog input is converted into four series of output pulsegroups, the number of pulses in each output group corresponding withdeeimal value of the digit in a corresponding order of the analog input.In the specific case assumed, the number of pulses respectivelyappearing on the output lines MBA-dill) of Converter 35 would be seven,three, five and nine.

The digital value of the output of Converter 35 for each of its cyclesis temporarily stored in the stages I to IV of register 25 inbinary-coded decimal form, such as l-2-4-2 code. The highest significantfigure is stored in stage I of the register and the three successivelylower significant figures are respectively stored in stages II to IV.When the And gates 31 are subsequently enabled by a C signal, theencoded output of register 25 is reu peated in the output device Stwhich may for example be a Flexowriter for reproducing the output intyped or punched-tape form. There is thus produced a read-out of theexisting output of the transducer 2314.. This phase of Operation of thesystem of FIGS. lA, IB is Completed when the stepping switch ll appliesa Reset signal D to clear the register 25.

The next phase of Operation begins when the stepping switch ll producesthe A signal of its next Cycle to step the scan switches IA-fl) to their#2 positions. For this switch position, the gain control 20 of amplifier22 has 1oeen preset by scanner 16 to multiply the analog output oftransducer ZBA as amplified by arnplifier 21 by the factor 1/6. Thus,for the same example above assumed, the analog input to Converter 35would be or 1.226 volts and the number of output pulses respectivelyapplied over lines dtlA-dfll) to stages I to IV of register 25 would beone, two, two and six.

After a time delay sufiicient to permit the Converter 35 to complete itscycle and for the divider analog value (1.226) to be set into stages Ito IV of the register 25, the B signal is effectively applied over lineBB to shift to the right and by one decimal place the value temporarilystored in the register. Thus, as now stored in stages II to V of theregister 25, the output of the transducer fvA has been in effect dividedby 60 in two steps; the first by change in gain of amplifier 22 toeffect division by 6; and the second by the one-step register shift toeffect division by 10. The time delay between production of signal B andits efective application as a shift pulse over line '7 of the register25 may be afforded by the delay devices 24.14.4343. Specifically, thedevices ZdA-ZlB may be monostable multivibrators Which are triggeredfrom their normal state by a sharp pulse derived by difierentiator Illfrom the leading edge of signal B. Upon reversion to their normalsta-te, after a period determined by their circui-t parameters, themultivibrators produce output signals utilized to shift the registercontents by one decimal place. To such shifted value in register 25,representing Meg of the existing output of transducer 23A, is added thetotal of such previously shifted Values as stored in the accumulator 23.Such addition is eected when the output gates 27 of the accurnulator 28are opened by the B signal on line BD after a time delay introduced bythe one-shot multvibrator 43 or other suitable delay device. The Bsignal, after further delay, introduced by the delay device 445, resetsall stages of accumulator 23 to zero.

Whether such sum or new total now temporarily stored in the register 25as an accumulator is transmitted to the read-out device 34 or istransmitted to the accumulator 23 depends upon the count registered inthe counter 32. First assuming that 60 counts have been made, the outputsignal appearing on line 45 of the counter 32 enables the gates 31 sothat the summation of the counts, each representing %0 of the transduceroutputs as checked at one minute intervals, appears in binary-codeddecimal form in the output device 34. In short, at hourly intervals, theaverage value of the output of transducer 23A for the prior hour is readout of the system. Also, upon the same assumption that 60 counts havebeen made, the output signal appearing on line 46 of counter 32 inhibitsinput gates 439 of the accumulator 28 so that the hourly average asstored in the register 25 is not transmitted or set into the accumulator23. The 60-count average is effectively removed from the register 25when it is cleared by the Roset signal D as transmitted over line 15.Thus, at the end of each 60-count cycle for transducer ZZ'iA, bothregister 25 and the accumulator 2% are at zero setting and the averagevalue of the outputs of that transducer for the previous hour appear inthe output device 34.

if, on the other hand, less than 60 counts have been registered bycounter 32, the signal on its output line 4-5 inhibits the input gatesFil of the output device 34. l-lowever, the signal on output line 46 ofcounter 32. enables the And gate 42.17 so that the C signal, as delayedby device 48, is transmitted to enable the input gates 49 of accumulator28. Thus, the new total temporarily stored in stages I to V of theregister is transmitted to the accuinulator 28. Such new total iseffectively removed from register 25 when clearcd by the Reset signal Dfrom the stepping switch Ill. T hus, at the end of any count which isless than 60, the output device 34 is blank, the register 25 is blank,and the sum of the count outputs of transducer ZA, as divided by 60, isstored in the acccumulator 28.

The next phase of Operation of the system of FIGS. lA, lB begins whenthe stepping switch Ill produces the A signal of its next cycle to stepthe scan switches IftA-ISD to their #3 position. For this switchposition, the gain control 20 of amplifier 22 has been preset tomultiply the analog output of transducer ESA as amplified by amplifier21 by the factor Thus, for the same transducer output value aboveassumed, the analog input to converter 35 Would be or 5.110 volts andthe number of output pulses respectively applied over lines 40A-40D tostages I to IV of register 25 would be five, one, one and zero.

After a time delay suhcient to permit the converter 35 to complete itscycle and for the divided analog value 5.110 to be set into stages I toIV of register 2 the B signal is effectively applied over line IEC toshift to the right and by three decimal places the value Originally setinto the register. Thus, as new temporarily stored in stages IV to VIIof register 25, the output of transducer ZSA has been in effect dividedby 1440 in two steps: the first by change in gain of amplifier 2.2 toeffect division by 1.44, and the second by the three-stageregister-shift to effect division by 1,000. The time delay betweenproduction of signal pulse B and its effective application as threeshift pulses to register 25 may be alforded by the delay devices26A-26D. Specifically, the -devices ZoA-Zoi) may be monostablemultivibrators which are triggered from their normal state by a sharppulse derived by ditferentiator 49 from the leading edge of pulse B.Upon reversion to their normal state, after periode determined by theirrespective circuit parameters, the multivibrators produce signalsutilized to shift the contents of the register 25 by three decimalplaces. For simplicity and clarity of explanation here, these delaydevices as well as delay devices 24A-24B are shown vwith a single orcommon output line 7. Actually and as later discussed in connection withFIGS. 7 and 8 .showing the register in more detail, these delay deviceshave a multiplicity of output lines to the various stages of theregister.

To the shifted value in register 25, reprcsenting 1/1440 of the existingoutput of transducer ZSA, is added the total of such previously shiftedValues as stored in the second accumulator 30. Such addition is effectedwhen the gates 29 between accumulator 30 and register 25 are opened bythe B signal on line HE after a time delay introduced by the one-shotmultivibrator 55 or other suitable delay devices. The B signal, afterfurther delay introduced by delay device 54, resets all stages ofaccumulator 30 to zero.

Whether the new total or sum now temporarily stored in register 25 istransmitted to the read-out device 54 or is transmitted to theaccumulator 30 depends upon the count registered in counter 33. Assumingthat 1440 counts have been made, the output signal appearing on line 55of the counter 33 enables the gates SI so that the surnmation of 1440-coun-ts, each representing 1/1440 of the output of transducer ZfiA, asmeasured at oneminute intervals, appears in binari-coded decirnal formin the output device 314. Upon the same assumption that 1440 counts havebeen made, the output signal on line 56 of counter 33 inhibits the gate57 so that the pulse C as transmitted over line MC and delayed by thedelay device 58 is ineffective to open the gates 5% between stages I toVII of register 25 and accumulator 50. The 1440 count average iseffectively removed from the register 25 when it is cleared by the Resetsignal D transmitted over line IS. Thus, at the end of the 1440 countcycle for transducer ZSA, both the register 25 and the accumulator 50are blank and the average value of that transducer for the previoustwenty-four hours appears in the output device 54.

If, on the other hand, less than 1440 counts have been registered bycounter 33, the signal on its output line 55 inhibits the input gates 51of the read-out device The signal on the output line 50 of the counter33 enables the gate 57 so that the C signal, `as delayed by device 58,is transmitted to enable the input gates 59 of the accumulator 30. Thus,the new total temporarily stored in stages I to VII of register 25 istransmitted to the accumulator 30. Such new total is removed fromregister 25 when cleared by the Reset signal D as applied to line 15.Thus, at the end of any count which is less than 1440, the output device34 is blank, the register 25 is 6 blank, and the sum of the countedoutputs of transducer ZSA as divided by 14-40 is stored in theaccumulator 30. From the preceding description, it should be apparentthat a record made by the output device 34 will show:

(a) at one-minute intervals the then existing output of transducer ZBA;(b) at hourly intervals, the average output of transducer ZSA for theprevious hour as Well as the then existing output; and (c) at dailyintervals, the average output of transducer ZSA for the twenty-fourhours as well as the average for the preceding hour and the thenexisting output.

With the electronic circuitry employed in Commercial embodiments of theinvention, all three phases of operation of the system of FIGS. IA, IBas above described are Completed in a very short time; for example, allthe operations performed from #1 to #3 positions of a particulartransducer are Completed within one second so that within the minuteintervals between successive measurements on a single transducer, thesame Sequence of operations may be similarly perforrned for manytransducers. In such case the system of FIGS. IA, IB is provided withadditional pairs of counters 32, 33 and accumulators 28, 30, one pairfor each additional transducer. In such system, however, the Componentsused in common for all transducers include the pulse generator 10,stepping switch II, scanner 16, converter 35, Shifting circuits 24A-24Band 26A-26D, register 25 and read-out device 34. When differenttransducers have different ranges, the scanner Id also appropriatelychanges the gain of amplifier 2Il, for purposes above stated-when thescan switch TiA (FIG. IC) transfers from one transducer to the next.

Except in respects below specifically discussed, the system shown inFIG. 2 is similar to that of FIGS. IA, IB. Since the correspondingelements have been identfied by the same reference characters, thepreceding description of FIGS. IA, IB is for the most part applicable toFIG. 2 and need not be repeated.

It will be be recalled in the system of FIGS. IA, IB the pulse output ofthe convertor was first introduced into stages I-IV of the register 25,was subsequently shifted either to stages II to V or to the stages IV toVII of the counter, and to such shifted count is added the content ofthe accumulator 28 or 30 for the #2 or #3 positions of the scanswitches. As will appear from the subsequent discussion of FIGS. 7 and8, this arrangement requires the module circuitry to be quite complex.In the system of FIG. 2, now described, the four groups of pulsesforming the output of converter 35 are steered directly either to stagesI to IV, to stages II to V, or to stages IV to VII depending uponwhether the particular phase of operations calls for a direct read-outof the instantaneous Vanalog value, a read-out or accumulation of thehourly average value, or a read-out or accumulation of the daily averagevalue. For the #2 or #3 positions of the scan switches, the contents ofthe accumulator 25% or 30 is transferred into register 25A before itreceives the output of converter 35. l

Referring to FIG. 2, the four output lines 40A-40D of converter 35 arerespectively connected to one of the input terminals of the And gatesoA-ol). The output terminals of gates 66A-d5i3 are respectivelyconnected to corresponding input terminals of stages' I to IV of theregister ZSA. The other input terminal of each of gates edAfldD isconnected to line ISF so that all of rthese gates are enabled by the Csignal of stepping switch II when the second switch 183 is in its #1position. The previously generated B'signal, after a delay introduced bythe delay device 67, initiates a cycle of the converter 35. Thus, thefour groups of pulses sequentially appearing on output lines 40A-40D ofthe converter `are respectively steered into stages I to IV of theregister 25A. Thus, as previously described in connection with FIGS. IA,IB, the binary-coded decimal value of the atomene four significantfigures of the existing analog input to the converter are temperarilystored in register Z'A and are transmitted for the til position of scanswitches lA-lll) to the read-out device The four output linesft-t'iAJttiD of Converter 35 are also respectively connected to one ofthe input terminals of a second group of And gates 68A-68D. The outputterminals of gates tSA-SD are respectively connected to correspondinginput terminals of stages ll to V of register ZSA. The other inputterminal of each of gates dtEA-oD is connected to line E33 so that allof this second group of gates are enabled by the B signal when the scanswitches including switch JB are in the #2 position. Thus, the fourgroups of pulses respectively appearing on output lines dA-4tiD ofconverter 35 are steered directly into stages ll to V of the register25A and consequeutiy the value set into the register corresponds,without need for Shifting, with lfifio of the analog input to amplifier22..

The four output lines ltlA-flltll) of Converter Se" are currentssupplied to the suinmation point '77 through selected resistors of eachof the groups of sumrning resistors 'IMT-'7215, 73A-75D, 'MA-741) and'75A-75D. The switching of reference currents through resistors '72A-72Drespectively is eifected by switches 76A-76D, preferably of thetransistor type shown in copending application Serial No. 95,714. Theswitches '75A-76D are respectively turned On by the signal from theassociated one of the four stages l to IV of the binary counter 78.Jl'lor example above given, the Values of reference currentsrespectively supplied to the junction point '77 by resistors arel,2,4,2, each tirnes l 3 arnphere.

Starting with the first decade counter 73 set at zero, as hereinafterdescribed, the state yof each of the switches 'MA-763), the state ofeach of the resistors '72A-'7ZD and the value of the total currentsupplied through that group of resistors to the summing junction '77 forup to the maximum of nine input pulses to counter 78 are shown by TableI below.

TABLE I Pulses Switches Rcsistors C'geat 76A 76B 760 76D 72.A. 72B 720721) Un xm 0 OFF OFF OFF OFF OFF OFF OFF OFF 0 1 ON OFF OFF OFF ON OFFOFF OFF 1 2 0FI ON OFF OFF OFF ON OFF OFF 2 3 ON ON OFF OFF ON ON OFFOFG` 3 4 OFF OFF ON OFF OFF OFF ON OFF 4 5 ON OFF ON OFF ON OFF ON OFF 56 OFF OFF ON ON OFF OFF ON ON 6 7 ON OFF ON ON ON OFF ON ON 7 8 OFF ONON ON OFF ON ON ON 8 9 ON ON ON ON ON ON ON' ON 9 also respectivelyconnected to one of the input terminals of a third group of And gatestiA-ei'l). The output terminals of gates 69A-69D are respectivelyconnected to corresponding input terminals of stages TV to Vil ofregister ESA. The other input terminal of each of gates tights-691) isconnected to line tlC so that all of this third group of gates areenabled by the B signal when the scan switches including switch 133 isin the #3 position. Thus, the four groups of pulses respectivelyappearing on output lines MDA-MED of the Converter are steered directlyto stages IV to Vil of register ZSA. Consequently the value set into theregister ZSA corresponds, without need for Shifting, with 1/1440 of theanalog input to ampliiier 22.

Thus, with the system of FIG. 2 as with the system of FIGS. 1A, IB, therecord made by the output device 34 will show at one-minute intervalsthe then existing output of transducer ZSA; at hourly intervals theaverage output of transducer 23A as well as its then existing output;and at daily intervals the average output of transducer 23A for theprevious twenty-four hours as well as the average for the preceding hourand the then existing output.

The circuitry of an analog-to-digital Converter 35 suited for use in thesystems of FIGS. IA, IB and 2 is schematically shown in FIGB. Thisciruitry is per se clairned in copending application Serial No. 74,523,flled December 8, 1960. The analog output current of amplier 22 isimpressed within the Converter upon the input circuit of acomparison-amplifier '7%i through a standard resistance 71. For purposeof explanation, it may be assumed that the maximum current traversingresistor Fil is nearly 10 milliarnperes and that resistor '71 is 1,009ohms. The unknown current through resistor '271 is eventuallyautomatically balanced by the surnrnation of reference For the exampleabove given, the Values of the reference currents respectively suppliedto the summing junction '77 through resistors '73A-'73D are 1, 2, 4, 2,each times iii-4 ampere. The switches 'WA-WD for turning on the currentfor the associated resistors 'BA-731) are respectively controlled by asignal from an associated one of the four stages I to IV of the counter81. With the counter 81 set at zero, the state of each of the switches'mA-WC, the state of each of the resistors 73A-73D and the total currentsupplied by that group of resistors to the surnrning junction '7'7incrementally changes in accordance with a table similar to Table Iexcept for change in the table headings of the reference charactersindentifying the switches and resistors and except that the multiplierfor the digits of the last column is l0 4 instead of l0 3 ainpcrezi.

The reference currents supplied to the summation point '7'7 through the1other two groups of resistors MA- 'M-D and '75A-'75D are similarlycontrolled by the switches tZA-SZD associated with counter 83 and byswitches 84A-34D associated with counter 85. The input pulses to counter33 progressively change the total output current of the group ofresistors 'MA-'MD by iucrements of 1 l{) 5 `arnperes from zero to apossible maximum of t 10-5 amperes and the input pulses to counter 85progressively change the total output current of the group of resistors75A-'75D lby increments of 11 l() 6 arnperes from zero to a possiblemaximum of 9 10"6 amperes.

Thus, by selective Operation of the switches of each of the four groupsof switches Unni-'7613; '79A-79D; SZA- 82D; S-tA-fliD), the totalbalancing current supplied to the summation point 77 in opposition tothe unknown analog current may be set anywhere in the range from zero to9.999 milliamperes to match the unknown analog current within 1 10-6amperes.

For purposes of explanation, it is now assumed that the analog inputcurrent through the standard resistor '71 is 3.596 ma. and is to beconverted to four gnoups of pulses with three puses appearing on outputline ZitiA of the decade counter '78, five pulses appearing on outputline dtlB of decade counter 81, nine pulses appearing on output line MCof decade counter 3 and six pulses appearing on output line ltlD ofdecade counter Starting with the counter 7% set at zero and ali of thecounters 813335 set at 9, the total current supplied to the junctionpoint 77 for the four groups of resistors is 0.999 ma. Counting pulses7as supplied over line 90A and through the then enabled gate 91, advanC-ethe counter '78 step-by-step, per Table I, until for the third pulse thetotal current for the first group of summing resistors 72A-72D is 3.000ma. Thus, the total current for all four groups of resistors is 3.999ma. which exceeds the Opposing analog current (3.596 ma.) and so etfectsa reversal of the output of the comparator-amplifier 79. Until suchreversal, the counting pulses passed through gate 91 to the counter 73are also passed by the gate 92. to the output -line ltlA of theConverter. The number of pulses supplied over line 40A to the registor25 of FIG. 1B or regist-or ZSA of FIG. 2 thus corresponds with thehighest significant digit of the unknown analog input current toConverter 35.

Upon such reversal of the Comparator-ampliiier output, the And gates 91and 92 are inhibited and the second counter til is set to zero. Thus,the next count for detenmining the next highest significant digit of theunknown analog current starts with the total current supplied throughthe four groups of surnming resistors at the value of 3.099milliarnperes for which the output of comparator-amplifier 70 reverts toits original state or sign of unbalance. When five successive Countingpulses on line 90A have been passed by the now enabled gate 93 to decadecounter 331, the total current passed by the second group of sumniingresistors 73A-73D has been stopped to 0.5000 ma. Thus, the total currentfor all four groups of summing resistors is now 3.599 rna. which againexceeds the unknown analog current (3.596 ma.) and so effects a .secondreversal of the output of comparator-amplifier 79. Since the gate 94 isenabled during this second counting interval, the five counting pulsespassed by the gate 93 to the counter til are also passed by gate 94 toappear on the output line 403. Thus, the number of pulses supplied overoutput line ltiB of the second decade counter til to the register 25(FIG. IB) or register 25A (FIG. 2) Corresponds with the next highestsignificant digit of the unknown analog input current to Converter 35.

Upon such second reversal of the output of arnplifier 70, the gates 93,94 are inhibited and the third decade counter 83 is set to zero. Thus,the next count Starts With the total current supplied through the fourgroups of su-nuning resistors at the value of 3.509 milliarnperes forwhich the output of amplifier 7 reverts to its original sign ofunbalance. When nine Counting pulses sequentiallly applied to/line 90Ahave been passed by the now enabled gate 95 to counter SS, the totalcurrent passed by the third group of resistors 74lA-74D has been stoppedto 0.090 ma. Thuls, the total current passed to the sumrning junction 77is now 3.599 Ina. which again exceeds the unknown analog current (3.596ma.) and so efiects a third reversal of the output of theConiparator-ainplifier 70. Since the gate 96 is enabled during thisthird counting interval, the nine Counting puises passed lby gate 95 tothe counter 83 are also passed by gate 96 to appear on the output line480 of the third decade counter 83. Thus, the number of pulses suppliedover output line fitiC to the register 2.5 (FIG. IB) or register ZSA(FEG. 2) corresponds with the third highest digit of the value of theunknown input current to Converter 35.

Upon such third reversal of the output amplier '70, the gates 95, 96 areinhibited and the fourth decade r and 35 to 9.

counter 85 is set to zero. Thus, the count of the fourth ecade startswith the total current supplied through the four groups of sumrningresistors at the value of 3.590 ma. for which the output of amplifierr-everts to its original sign of unbalance. When six counting pulsessequentially applied to line 901% have been passe-d by the now enabledgate 97 to counter 85, the total current passed by the four-th group ofsumrning resistors A- 759 has been stopped to 0.006 ma. Thus, the totalCurrent passed to the summing junction 77 lis now 3.596 rna. whichmatches the unknown analog input current to four signincant digits. Theaniplifier 'Til has itself a small input bias so that when such matchingis obtained, the amplifier output reverses to disable the gates 97, 98and so prevents any further pulses on line 9tiA from being applied tocounter or to the output line stil). Since the gate 98 has remainedenabled during this fourth counting interval, the six counting pulsespassed by gate 9'7 to counter 85 have also been passed by gate 93 toappear on the output line 4501). Thus, the number of pulses suppliedover output line 401) of the fourth decade counter 35 to the register 25or 25A corresponds with the fourth highest digit of the unknown value ofthe analog input Current to Converter 35.

En brief, by the end of a `complete Cycle of the converter 35, its fourdecade counters '73, 81, 83, 85 have in effect converted the analoginput to the Converter into four sequentialiy-produced groups of outputpulses with the number of pulses on the successive groups respectivelyCorresponding, in descending order and as appearing on output linef-tiA-fitlD, with the first four significant digits of the analog input.

There is now described how the gates 91 to 93 and the counters '78, 81,and 85 of Converter 35 are conditioned by the Start pulse .supplied bythe stepping switch til of FIG. lA or FIG. 2 to line ESA of theConverter and are con-ditioned by the five-stage ring Counter litt) toeffect the four Counting Cycles above described. Prior to initiation ofa Cycle of the Converter, the stages of the counter ftiti have been setto their initial states for which the first stage is On and the otherfour stages are Od. The application of the ADC Start pulse B to the:line ESA of the Converter performs at least two operations. The firstis to set all of the counters 78, 811, 83 The second is that the pulseas passed by the Or gate 192 to the line 3.06 which, as in manner laterdescribed, turns Stage H of the ring counter to On and Stage f of thering counter to Off. The Start pulse B as applied over line ISA alsoturns the fiip-fiop litt to the On state if not already in that state.With the first stage of :the ring counter turned Off, the output of thatstage as appearing on line ldIA enables the gate E04 so that the Clockpulses produced by the generator ltiS are passed to the line 919. Theirutial pulse passed by the gate 194, after a delay introduced by thedelay devices 197, lllltl and ltlll and as inverted by inverter 135 istransmitted by line 9A to the And gate 91 which has been enabled by theturning On of the second stage of the ring counter. This initial pulsechanges the setting of the counter '73 from 9 to 0. At that time,:because of the state-of the fiip-flop ll-il, the Converter-output gate92 is inhibited by the level on line 9913. Thus, this initial or zerocount pulse does not appear as a count on the output line -GA. With theCounter 73 so reset, the total sumrning Current .supplied to the jnction77 is less than the assurned analog input to the comparator-amplifier79. The first count pulse, after a delay introduced by the delay device107 and as inverted by inverter is also applied over line to the gate109. Thus, the arnplifier output is passed to reverse the state of theflip-fiop 112. The resulting output of tlip-flop 112 on line 117 enablesthe And gate Hii so that the first count pulse is effective to reversethe state of the flip-fiop ltif. The resu'lting output on line 993 nowprovides another enabling level for the output gate 92. Thus, the firstcount pulse, as further k the Off state.

aie'aeaa delayed by the delay devices llltl, Tillit and as appearing online GEA, now serves as a counting pulse supplied through gate 911. tothe cou. i' 'f and as an output pulse as passed by :gate to 'ole line401%. The following counting `pulses are similarly applied over linelflA to the gates 91 and until, as previously described, the output ofthe comparator 753 reverses in sign.

Such reversal of the comparator upon completion of the count for thefirst decade counter '73 changes the output of gate 109 to turn Off theflip-fiop 312 so to enable the gate till. The next pulse, which is thezero-count pulse, is applied over line 123 to the now enabled gate Theresulting output of gate lid is applied to line 118 and thence throughthe Gr gate IlilZ to the line lil/6. This initial or zero-count pulse asapplied to the lil stage of ring counter Tdi? produoes on line 119 anoutput which enables input gate 96 of the second decade counter 81 andproduces on line 120 an output which turns Off the Ti stage of the ringcounter lliiii. Again, as previously described, the output of amplifier7il reverses in sign so that the first count pulse is elfective toreverse the flip-liop ilfllll so that its output on line WB provides asecond enabling input of And gate 594. This first count pulse is alsoeffective, as later appearing on line QtlA, to pass through gate 93 tostep the counter til from zero and also to pass through output gate 94to appear on output line -flB of the second decade counter 81. Thesubsequent counting pulses are similarly applied over line gilA to thegates 95, 94 until, as previously described, the output ofcomparator-amplifier 70 again reverses in sign.

The same sequence of events occurs for the counting by the next twodecade counters 83, 85. Upon reversal of the ampliier output resultingfrom the last count pulse to counter 85, the switching pulse appearingon line llf and passed by gate 102 to line 106 is effective, as nowdescribed, to result in a Sequence ending with stage l of the ringcounter Mit) in the On state and stage V in In this case, as well as forthe other reversals of amplifier output, the switching pulse appearingon line Title is applied to all stages of the ring counter but only thatstage which at that time follows an On stage is switched On and thatstage in turn switches Off the preceding stage. For example, during theperiod for which counter is functioning, the V stage of the ring counter1% is On and its output appearing on line 121 conditions the I stage ofthe ring counter so that when the arnpliier reverses for the last count,the switching pulse appcaring on line file is effective to turn the Istage of the ring counter On. The resulting output of stage I of thering counter as appearing on line lflll is effective to turn Off stage Vof the ring counter. This same output as appearing on line TGSA inhibitsthe gate TM to terminate the passage of clock pulses from the pulsegenerator WS to the line WA. This ends one cycle of operation of theanalog-to-digital Converter 35.

in the preceding discussion, no mention has been made of the output lineflo from gate TM- to the flip-op 13.2 or to the gate lid between theiiip-flops lltlll, 112. A puise on line flo presets the flip-fiop 112 toits reversed state and the resulting output on line 122 enables the gate113 so that the same pulse, as delayed by device Htl, is passed by thegate lll to the fiip-fiop illlil. The resulting output on line WBinhibits the output gates 92, f'fll, 96 and 955 for all pulses exceptthe counting pulses for each decade. The number of such counting pulsesfor each decade, as should be apparent from the proceding discussion,may vary from one to nine as required to effect a reversal of output ofthe amplificr W. The presetting of the ifip-flop 112 by a pulse on lineflo is to a state confirmed by the subsequent application of the samepulse to gate 109 when the total of the summing currents has notexceeded the unknown analog current. The outputs on lines 117, 122 fromthe fiip-liop lIlZ are complementary so that as applied through gatesllllfi, 113 respectively to the opposite sides of the flip-tlop Till,they fi. lig reproduce in Flip-flop llfllf the same state as flip-fiop112 yet provide for time displacement of the signals respectivelyappearing on lines llIiS and MEE.

FTG. 4 shows a typical one of the stages of the register of HG. 2. Eachof the four rnodules W, X, Y, Z of each stage, in detail shown in FLG,5, is a bistable multivibrator or flip-flop circuit which, for purposesof explanation, is to be considered 011 when a binary 1 is stored in theleft-hand side and a binary 0 is stored in the righthand side. Eachstage also includes a counter-advance module shown in-FIG. 6. The stateof each of the four modules of each stage for from one to nine counts isshown in Table ll below:

TABLE ll Modules pulses W X I Y z V'r 1 ON OFF oFF oF'r` OFF 2 our1 ONour our1 orn s ON oN Ohr OFF OFF i Om` OFF ON OFF oFF 5 ON ON OFF ON v-Ons s OFF OFF oN ON OFF 7 ON Ohr ON oN OFF s oss ON ON oN oss s oN ON ONoN OFF Raset OFF OFF OFF oFF OFF As indicated by the last or lowest rowof Table II, the reset pulse D as applied by lines f' to modules W, X,Y, Z of all stages insures that all of them are turned Off before theConverter 35 begins its cycle. If during a cycle of Converter 35 nopulse is applied to any particular one of the regsiter stages from thecorresponding output line of the Converter, all of the modules W, X, Y,Z of that stage remain Off so that the binary-coded decimal set intothat stage and represented by the state of the output lines 125-128 iszero.

lf and when a first pulse is applied to the W module of a register stagefrom a corresponding one of the output lines tlA-Kil) of the Converter,the W module is turned On (first row of Table lil) so that its output online 11.25 of the stage corresponds with the binary-coded decimal valueof l.

lf and when a second pulse is applied to the W module Of the stage, theW module is turned Off and its output appearing on line 129 is efectiveto turn On the X module (second row of Table ll). The output of module Xas appearing on output line 126 of the stage corresponds with thebinary-coded decimal value of 2.

lf and when a third pulse is applied to the W module of the registerstage, it is again turned On. Since the X module remains Gn (third rowof Table II), the outputs on lines 125, 1% of the stage correspond withthe binarycodec!L decimal value of 3.

fr" and when a fourth pulse is applied to the W module, it is againturned Gff and the output of its line 129 turns Qff the X module. Theresulting output of the X module as appearing on line 13% turns Gn the Ymodule whose output as now appearing on. output line 127 of the stagecorresponds with the binary-coded value of 4.

At `this point in the counting, the outputs of the Y and Z modules asappearing on lines 1132, 133 of the counter-advance module condition itfor being turned On it' and when .a fifth input pulse is applied to theW module.

if and when a fifth pulse is applied to the W module, it is again turnedOn and its output appearing on line 151 to module T effects a series ofevents now described. The output of module T appearing on line 134 turnsOn the X module and the output of module T appearon line E35 turns Offthe Y module. The resulting output Of the Y module as appearing on line136 turns s,197,eea

On the Z module. The T module is inactive for any subsequent pulses inthe count. Thus, and as shown in the fifth row of Table II, theapplication of the fifth pulse, Combined with the action of thecounter-advance module T, results in the W, X and Z modules being set tothe On state. Their outputs as appear-ing on lines 125, 125 and 128correspond with the binary-coded decimal value of for the stage.

From the preceding description and Table II, it should be apparent thatfor application of any further 'input pulses, up to 9, to the registerstage from the corresponding output line of Converter 35, there iscorrespondence between the number of input pulses and the binary-codeddecimal value represented by the outputs of the W, X, Y, Z modules ofthe stage as appearing on the output lines 125 to 128.

Although all output stages of the register 25A are set to zero by resetpulse D after Converter 35 has completed a cycle for the #2 and #3positions of the scan switches 17A-17D, the transmission into theregister of the contents of the accuinulator 28 or 311 before any pulseis received from the Converter 35 in effect advances each stage of theregister to the binary-coded decirnal value stored in the correspondingstage of the accumulator. The output pulses subsequently receive-d fromConverter 35 then further advance the count in the register stage inaccordance with Table II up to the maximum count 9. The in-terstagecarry lines 137 become involved when the digital value transferred to astage from the accumulator plus the number of pulses subsequentlyreceived from the Converter exceed the value 9. Assuming, for example,that a particular stage has been advanced to the output value 6 by atransfer thereto from the accumulator and that four pulses aresubsequently supplied to the register from the converter for the firstthree of these pulses, the count proceeds from 7 to 9 as shown in TableII. For the fourth of these pulses, the output of the Z module asappearing on its output line 137 is eifectively carried over to the Wmodule of the next higher order stage as an additional count for thatstage.

The basic circuitry of the counter modules of FIG. 4, per se known, isshown in FIG. 5 and now briefly described. Each counter module isfundamentally a bistable flip-flop circuit comprising a pair oftransistors 1411, 142 which are cross-connected by the feedback lines143, 144 so that when either transistor is turned On, it in turnswitches the other transistor Off. When a reset pulse appears on inputline of the module, the transistor 141 is turned Off and in turnswitches the transistor 142 to On. For this state of the transistors,the line 143 is negative with respect to ground and the line 144 isessentially at ground potential. Because of the inverters 145, 147, thejunction of diode 149 and capacitor 15% is essentialiy at groundpotential and the junction of diode 151 `and capacitor 152 is negativewith respect to ground. Also for this state of the transistors, thejunction of capacitor 1511 and resistor 153 is essentially at groundpotential and the junction of capacitor 152 and resistor 155 is negativewith respect to ground. When a negative signal is applied to thejunction of diodes 149, 151, it is effective to turn On the transistor141 which in turn switches Ofl the transistor 142.

Now assurning that transistor 141 is On and transistor 142 is Off: thejunction of diode 149 and capacitor 1511 is negative with respect toground; the junction of diode 151 and capacitor 152 is essentially atground potential; the junction of capacitor 151) and resistor 153 isnegative with respect to ground; and the junction of capactor 152 andresistor 155 is essentially at ground potential. When a negativepotential is now applied to the junction of the diodes 149, 151, it iseffective to switch transistor 1412 to On and this transistor iseifective in turn to switch the transistor 141 to Oif.

In brief, whenever a negative signal is applied to the junction of thediodes 1459, 151, the complementary outlid puts of the module arereversed regardless of the states of the transistors. The networkcomprising the diodes 149, 151, capacitors 15%, 152 and the inverters145, 1117 provide a stecring circuit which directs the negative inputsignal to turn On whichever transistor is then Off and the switchedtransistor in turn switches the other transistor to On.

The sources for the negative signals above discussed depend upon thelocation of the module in the counter register 25A. For the W module ofa particular stage, one of the input lines to the junction of diodes149, 151

is from a corresponding one of the output lines litlA-Ltt'tl) of theconverter and the other input line is the carry line 137 from the nextlower stage. For the X, Y and Z modules, there is only one source ofnegative input signals, i.e., lines 129, 1311, respectively. For all ofthe modules W, X, Y, Z, there is a line 174 from the correspondingmodule of one or the other of the accumulators 28 or 311 for transfer ofits contents into the register 2.5A.

The internal circuitry of a suitable counter-advance module T is shownin FIG. 6. The circuitry of module T is basically the combination of adifferentiator, an And gate and an implifier. A negative signal on theinput lines 132, 133, the And gate formed by the diodes 150, 151, andtransistor 152 will produce an output upon application of a groundingsignal on line 131. Such signal as differentiated by capacitor 153 andapplied to the base of transistor 162 completes the enabling of the Andgate. Before such gate is turned On, the amplifiertransistor .154 is inslightly conductive state with current flowing from the positiveterminal of battery through resistors 158, 167, transistor 154- andresistor 166. Current also flows from the positive terminal of battery165 through resistor 153, diodes 159 and resistor to the negativeterminal of the battery. Because of the low forward-resistance of diode159, the potential at point 171 is essentially the same as that of thejunction between resistors 157, 155. Thus, the capacitor 172 is charged`and has the poling indicated. When the And gate is momentarily enabled,as above described, the transistor 154 becomes highly conductive becauseof the forward bias derived from resistors 165, 173 and 183, and theVresulting increased flow of current through resistor 157 furtherincreases the charge of capacitor 172. Upon cessation of thedifferentiated pulse, the transistor 162 reverts to the conductivestate, disabling the And gate whereupon transistor 164 reverts to itsslightly conductive state. Upon such reversion, the potential of point`171 is more positive than the potential of the junction betweenresistors 157, 158 so that there is no current conduction through diode159. Consequently, the discharge of capacitor 172 produces a positiveoutput pulse on the lines 134, 135.

One stage of the shift counter register 25 of FIG. IB is shown in FIG.7. lt is similar to the counter stage shown in PEG. 4 but each of its W,X, Y, Z modules, as shown in detail in FIG. 8, has two additional inputshiftsteering lines 175, two additional output shift steering lines 175tan-d a shift pulse line 27 (FIG. l-B) comprising lines 27A, 273, 270.For counting, the negative countenabling signal appears on line Z7C toenable the gates 177, 17%, MSA and 1417A. For Shifting, a negativeshift-enabled signal appears on line 27A to enable gates 179, 1811, 181and the shift pulse subsequently appearing on line 27B is passed by gate179 and inverted by inverter 791 and applied to the junction of diodes149, 151. The shift pulse is steered by gates 180, 1131 to transfer intothe module the binary contents of the corresponding module of the nexthigher order stage of the register and simult-aneously to transfer outof the module, by the complementary steering line 175, 176, its binarycontents of the corresponding module of the next lower order stage. Fortransfer into the module, after the counting and Shifting, of the binarycontent atomene stored in a corre'sponding module of the accumulator 23or Sil, there is provided a pair of gates ZlA, 29/3 and a ditferentiatorcircuit including diode 134 and capacitor 135. With one of the other ofgates ZDA, 2% enabled by the complementary outputs of the accumulatormodule and a B signal on line 1353, the differentiation of the B signalby capacit-or lrS produces a transfer shift pulse Iapplied to thejunction of diodes 149, 1511. This produces in the register module areproduction of the binary content of the accumulator module.

.The counter-advance module TA used in the shif counter register stageof HG. 7 may be the same as that shown in FIG. 6 including the inputline IC to which is applied an inhibit signal precluding advance of thecount in the stage when the shift-steering lines 175, 176 1are enabled.This module as used in the count stage of FIS. 1 and in the register 25Aof FlG. 2 need not include this input line 270 There is now discussedanother mode of operating the systems of FiGS. lA, lB and FIG. 2 to readout the average of the outputs of a plurality of transducers in rapidsuccession applied to .the amplifier `means 21, 22. With the scanswitches llA-Jt-D .set in their #2 position, for example, the switchIthil is thrown to its dotted line position (FiG. IA) so that the Apulse output of the stepping switch lll is applied to the scanner ldA tostep the scan switch 189 for each cycle of the stepping switch. Theswitch f? is thrown to its dotted line position so that the Reset pulsesD of the stepping switch lil yare not applied to the register 25 of FlG.1A or the register 25A of FlG. 2.

Assuming the switch MQ has twelve contacts respectively connected to acorrespondng number of transducers ZBA et seq., the gain of the scalingamplifier 223 is set to effect division by the factor For each twelvesuccessive cycles of the switch llll, the

goutputs of the twelve transducers 23A et seq. are in succession appliedto arnplifier lo. For each of these twelve cycles, the Converter 35 isstarted by the B pulse of the steping switch lil as above described, andthe output of the connected transducer is set into the register 25 orZKSA with a displacement corresponding with a division by the factor 10.As the coded output of each transducer is in turn entered into theregister, it is there added to the accumulation therein of the previousoutputs of the series.

With the counter 32 preset for twelve counts, the application of thetwelfth B pulse over its input line lt-B produces on line d an outputwhich enables the gates 31 so that the summ-ation of the twelvetwice-divided outputs of the transducer as appearing in stages I to IV'of the register are transferred to the output device M as abinary-coded signal representing the average of the outputs of thetransducers scanned by switch 189. The output of counter 32 after adelay introduced by delay device 1% is applied through switch 187 as aReset pulse which clears the register.

For this mode of Operation, the transfer of the contents of vtheregister to accumulator 28 is avoided by Preventing the B pulses fromenabling the gates 4%. rIhis may be accomplished by Opening the switchllll in output line dd of counter 32. v

Although the invention has beendescribed in connection with preforre-dforms thereof, it will be understood that it comprehends modificationswithin the scope of the appended claims.

What is claime'd is:

ll. A system for producing a binary-coded digital output representingthe average of a predetermined number of successive analog Valuescomprising summation means including counter means havingnormal-digit-position stages and at least one stage of lower order,means for dividing the successive analog Values each by a first factorrelated to said predetermined number thereof, Converter means fortransforming each analog Value as divided by said first factor into abinary-coded signal consisting of groups of pulses, the number of pulsegroups corresponding with said sumber of normal-digit-positions of saidcounter means, and the number of pulses in each group respectivelycorrcsponding with the numerical value of a corresponding one of thesignificant digits of said analog value, means for entering each of saidbinary-coded signals in said counter means with displacement from itsnormal digit position in direction and extent corresponding withdivision by a second factor, the product of said first and secondfactors corresponding with said predetermined number of analog Values,accurnulator means having a number of stages exceeding the number ofnormal-digitposition -stages of said counter means, the number of stagesin excess being related to the| second factor, a first gating means fortransferring the twice-divided digital value of successive binary-codedsignals from and back to the counter means Via the accumulator means foraddition to the accumulated digital Value of previously similarlytransferred binary-coded signals, read-out means, and a second gatingmeans between said read-out means and said counter means effective uponentry in said counter means of said predetermined number of binarycodedsignals from the Converter means for transfer to the read-out means fromthe normal-digit-position stages of the counter of a bnary-coded signalcorresponding with the average of said predeternlined number of analogValues.

2. A system as in claim ll in which the means for dividing the analogValues by the first factor comprises an amplifier With binary-codedfeedback resistors for presetting the amplifier gain in dependence uponthe number of the successive analog Values to be averaged.

3. A system as in claim ll in Which Vthe counter means is a shiftcounter, in which the binary-coded signals are initially entered in saidnormal-digit-position stages of the shift-counter means, and in Whichtheir said displacement is elfected by means producing and applying tothe shif counter shift pulses in number corresponding with said seconddviding factor.

d. A system as in claim 1 in which said displacement of the binary-codedsignals is effected by gating means which steer said binary-codedsignals from the converter means into those stages of the counter meanscorresponding with division by said second factor.

5. A system as in claim Il in which each stage of the counter meanscompriscs four counter modules having binary-coded decimal outputs, anda counter-advance module, said counter-advances module comprising anamplifier, a differentiator, and three And gate elements, two of saidAnd gate elements being energized by outputs of two of said countermodules and the third of said And gate elements being energized by anoutput of another of said modules as dilferentiated by saiddifferentiator, the concurrent energization of all three of said Andgate elements producing a delayed pulse on an output line of saidamplifier to affect the state of certain of said counter-modules toprovide an advance in the Value of the joint output of all of saidcounter stages in steps of 1 from 0 to 9 for successive pulses of one ofsaid groups of pulses.

d. A system as in claim l including a second accumulator means having anumber of stages exceeding the number of normal-digit-position stages ofsaid counter means, the number of stages in excess being related to adifferent second factor, and a third gating means for transferring atwice-divided digital value of successive binary-coded signals from andback to the counter means Via the second accumulator means for additionto the accumulated digital value of previously similarly transferredbinary-coded signals, said second gating means between the read-outmeans and said counter means being effective after entry in said countermeans of a second predetermined number of binary-coded signals from theConverter means for transfer to the read-out means from the normal-digitposition stages of the counter of a binary-coded signal correspondingWith the average of the second predetermined number of analog Values.

7. A system for producing a binary-coded digital output representing theaverage of a predetermined number of successive analog Values comprisngsummation means including counter means having normal-digit-positionstages and at least `one stage of lower order,

means for dividing the successive Values each by a first factor relatedto said predetermined number thereof, Converter means for transformingthe divided analog Values into a succession of binary-coded signals,each consisting of groups of pulses, the number of pulse groupscorresponding With the number of said normal-digit-position stages ofsaid counter means, and the number of pulses in each group being from to9 depending upon the numerical value of a corresponding one of thedigits of the analog input of the Converter means,

means for entering each of said binary-coded signals in said countermeans with displacement from its normal-digit-position in direction andextent corresponding With rdivision by a second factor, the product ofsaid first and second factors corresponding with said predeterrninednumber of analog Values,

said counter means comprisng four counter modules having binary-coded-decimal outputs,

and a eounter-advance module, said counter-advance module comprisng anamplifier a diiferentiator, and

three And-gate elements, two of said And-gate elements being energizedby the outputs of two of said counter modules and a third of saidAnd-gate elements being energized by the output of another of saidmodules as diiferentiated by said differentiator, the concurrentenergization of all three of said And-gate elements enabling theAnd-gate and resulting in a delayed pulse on an output line of saidamplifier to effect the state of certain of said counter modules to provide an advance in the value of the joint output of all of said counterstages in steps of 1 from 0 to 9 for successive pulses of one of saidgroups of pulses,

said delayed pulse being derived from a network including a rectifier,

a capacitor,

resistance means traversed by the output current of said capacitor forcharging of said capacitor through said rectifier, and a circuitmaintaining conduction of said rectifier except upon Sudden decrease inoutput -of said amplifier occurring when said And-gate is disabled,

the output line of the amplifier being connected to the junction of saidcapacitor and said rectifier means,

said rectifier means becoming non-conductive upon said sudden decreaseof output current of said amplifler whereupon the discharge =of saidcapacitor produces a pulse on said output line.

References Cited by the Examiner UNITED STATES PATENTS 2,775,754 12/56Sink 340 347 MALCOLM A. MORRISON, Primary Examner.

LLOYD W. MASSEY, Examiner.

7. A SYSTEM FOR PRODUCING A BINARY-CODED DIGITAL OUTPUT REPRESENTING THEAVERAGE OF A PREDETERMINED NUMBER OF SUCCESSIVE ANALOG VALUES COMPRISINGSUMMATION MEANS INCLUDING COUNTER MEANS HAVING NORMAL-DIGIT-POSITIONSTAGES AND AT LEAST ONE STAGE OF LOWER ORDER, MEANS FOR DIVIDING THESUCCESSIVE VALUES EACH BY A FIRST FACTOR RELATED TO SAID PREDETERMINEDNUMBER THEREOF, CONVERTER MEANS FOR TRANSFORMING THE DIVIDED ANALOGVALUES INTO A SUCCESSION OF BINARY-CODED SIGNALS, EACH CONSISTING OFGROUPS, OF PULSES,THE NUMBER OF PULSE GROUPS CORRESPONDING WITH THENUMBER OF SAID NORMAL-DIGIT-POSITION STAGES OF SAID COUNTER MEANS,A NDTHE NUMBER OF PULSES IN EACH GROUP BEING FROM 0 TO 9 DEPENDING UPON THENUMERICAL VALUE OF A CORREPONDING ONE OF THE DIGITS OF THE ANALOG INPUTOF THE CONVERTER MEANS, MEANS FOR ENTERING EACH OF SAID BINARY-CODEDSIGNALS IN SAID COUNTER MEANS WITH DISPLACEMENT FROM ITSNORMAL-DIGIT-POSITION IN DIRECTION AND EXTEND CORRE-D SPONDING WITHDIVISION BY A SECOND FACTOR, THE PRODUCT OF SAID FIRST AND SECONDFACTORS CORRESPONDING WITH SAID PREDETERMINED NUMBER OF ANALOG VALUES,SAID COUNTER MEANS COMPRISING FOUR COUNTER MODULES HAVING BINARY-CODEDDECIMAL OUTPUTS, AND A COUNTER-ADVANCE MODULE, SAID COUNTER-ADVANCEMODULE COMPRISING AN AMPLIFIER A DIFFERENTIATOR, AND THREE AND-GATEELEMENTS, TWO OF SAID AND-GATE ELEMENTS BEING ENERGIZED BY THE OUTPUTSOF TWO OF SAID COUNTER MODULES AND A THIRD OF SAID AND-GATE ELEMENTSBEING ENERGIZED BY THE OUTPUT OF ANOTHER OF SAID MODULES ASDIFFERENTIATED BY SAID DIFFERENTIATOR, THE CONCURRENT ENERGIZATION OFALL THREE OF SAID AND-GATE ELEMENTS ENABLING THE AND-GATE AND RESULTINGIN A DELAYED PULSE ON AN OUTPUT LINE OF SAID AMPLIFIER TO EFFECTE THESTATE OF CERTAIN OF SAID COUNTER MODULES TO PROVIDE AN ADVANCE IN THEVALUE OF THE JOINT OUTPUT OF ALL OF SAID COUNTER STAGES IN STEPS OF 1FROM 0 TO 9 FOR SUCCESSIVE PULSES OF ONE OF SAID GROUPS OF PULSES SAIDDELAYED PULSE BEING DERIVED FROM A NETWORK INCLUDING A RECTIFIER, ACAPACITOR, RESISTANCE MEANS TRAVERSED BY THE OUTPUT CURRENT OF SAIDCAPACITOR FOR CHARGING OF SAID CAPACITOR THROUGH SAID RECTIFIER, AND ACIRCUIT MAINTAINING CONDUCTION OF SAID RECTIFIER EXCEPT UPON SUDDENDECREASE IN OUTPUT OF SAID AMPLIFIER OCCURRING WHEN SAID AND-GATE ISDISABLED, THE OUTPUT LINE OF THE AMPLIFIER BEING CONNECTED TO THEJUNCTION OF SAID CAPACITOR AND SAID RECTIFIER MEANS, SAID RECTIFIERMEANS BECOMING NON-CONDUCTIVE UPON SAID SUDDEN DECREASE OF OUTPUTCURRENT OF SAID AMPLIFIER WHEREUPON THE DISCHARGE OF SAID CAPACITORPRODUCES A PULSE ON SAID OUTPUT LINE.